As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory device (DRAM) or static-random-access-memory device (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
In particular, SRAM memory cells suffer stability problems as cell size is reduced. To function properly, the SRAM memory cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the charge pulse generated as the pass transistor turns on must not flip the voltage level at the output nodes. Usually this problem is controlled by adjusting the width-to-length (W/L) ratios of the driver transistor relative to the access transistor. The ratio of the W/L values of the two transistors is known as the cell ratio and is commonly specified to be at least 3.0 or larger.
One technique to reduce SRAM memory cell dimensions and to maintain cell stability is to split the word line over the cell. The word line controls read and write functions to the cell by turning the access transistors on and off. By splitting the word line into two separate lines, a more symmetrical cell layout is possible while at the same time maintaining a high cell ratio.
However, even with the foregoing improvements in memory cell design, a need remains to further reduce the overall cell dimensions. Although split word line designs reduce the area of the cell, fundamental manufacturing limitations remain. Active surface regions of the cell must be made available for the interconnection of leads providing supply and ground voltages to the cell. In addition, active surface area must be available for the formation of transistors providing read and write functions for the cell. Simple downsizing of components can only be pursued to the limit of the line-width definition capability of the manufacturing process. Once the line-width definition limits are reached, new design methodology must be employed if further reduction in memory cell area is to be achieved.